This invention relates to radio communications systems, frequency synthesizers, and specifically improving tune time and reducing phase noise in a phase locked loop that may be used in a frequency synthesizer.
Phase locked loops are commonly used to provide a precise, stable frequency. A phase locked loop (PLL) can be used in a frequency synthesizer as a local oscillator in a receiver and in a transmitter to generate an output signal having a selectively variable frequency. The basic elements of a phase locked loop include a voltage controlled oscillator (VCO) for producing an output signal with a controlled frequency, a phase detector for comparing the phase of the output signal with that of a predetermined reference signal and for producing an error signal representing the detected phase difference, and a loop filter for filtering the error signal and coupling it to the VCO to controllably adjust the output signal frequency.
A design tradeoff for loop bandwidth exists between tune time and phase noise in a phase locked loop. In applications such as frequency hopping transmitters and receivers, the frequency of a PLL frequency synthesizer must be changed quickly. For fast frequency changes, it is desirable that the PLL loop filter have a wide bandwidth. With the large number of noise contributors in a PLL this wide bandwidth results in poor noise performance. There is an optimum bandwidth for noise performance, which is often a smaller bandwidth than what is required for tune time. Once a new frequency is attained and the PLL is locked it is desirable to have a narrow loop filter bandwidth to reduce phase noise that affects transmitter and receiver performance.
To achieve the tune time and noise performance in many systems today, two separate PLLs are required. Only one PLL is used at time, the other is tuning during the dwell time. This is commonly referred to as a ping-pong solution. This solution allows the loop bandwidth to be designed for optimum noise performance and poor tune time performance since the dwell times are typically much longer than the tune time requirements. The hardware has to switch between the two loops to achieve the desired tune time. This solution ha a hardware impact of doubling the circuitry required to achieve the desired performance.
Another approach using two separate bandwidths is to switch between a wide bandwidth fast filter for fast tuning and a narrow bandwidth slow filter for operation with low phase noise. However switching introduces voltage transients that render the VCO output unstable for a length of time and the output is thus not usable until the VCO frequency stabilizes. The transients usually result from an inability to maintain a constant DC voltage level on a capacitor in the loop filter/integrator in both wideband and narrowband modes. The settling time may be too long for use in a frequency hopping system.
Another design to reduce tune time and phase noise has utilized a phase locked loop that has the capability to change loop bandwidth as the error frequency becomes small. There are limitations with this approach. The gain bandwidth is changed but the phase response of the loop remains unchanged. This limits the range over which the gain bandwidth of the loop can be changed.
What is needed is an approach for reducing phase locked loop tuning time and phase noise that offers fast tuning adequate for frequency hopping applications while meeting phase noise requirements.